In a pure capacitor, the current leads the voltage by 90° (a quarter cycle). The reason: current is highest when the capacitor is empty (voltage zero) and drops to zero when the capacitor is fully charged (voltage maximum), so current always "arrives first." Memory hook: "CIVIL" - in a Capacitor (C), I comes before V.
The blue current curve reaches its peak before the red voltage curve. Current is maximum where voltage crosses zero, because current depends on how fast the voltage changes (i = C·dV/dt), giving a 90° lead.
Your doubts, answered
Does current lead or lag the voltage in a capacitor?
In a pure capacitor the current LEADS the voltage. This is opposite to an inductor, where current lags. Use the trick CIVIL: for C (capacitor), I (current) comes before V (voltage). So current is ahead, voltage is behind, by 90°.
Why exactly 90° and not some other angle?
Because the capacitor's charge follows the voltage: q = CV. Current i = dq/dt = C·dV/dt. If V = V0 sin(wt), then i = C·V0·w·cos(wt) = i0 sin(wt + 90°). The cosine is exactly 90° ahead of the sine, so the phase difference is exactly 90° for a pure (ideal) capacitor.
How can current flow if no charge crosses the gap between plates?
No charge jumps the gap. But as AC changes, charge keeps piling onto one plate and leaving the other. This back-and-forth movement of charge in the wires IS the current. When the voltage is changing fastest (near zero volts), the charge moves fastest, so current is maximum there.
Why is the current maximum when voltage is zero?
Current depends on how FAST the voltage changes, not on its value: i = C·dV/dt. A sine wave changes fastest as it crosses zero and changes slowest (flat) at its peak. So current peaks when V = 0 and current is zero when V is at its peak. That gap between the two peaks is the 90° lead.
⚠️ The NEET trap ✗ Current lags the voltage by 90° in a capacitor (mixing it up with an inductor). ✓ Current LEADS the voltage by 90° in a capacitor. Inductor = current lags; Capacitor = current leads. 🧠 Remember CIVIL: in L current lags (V then I), in C current leads (I then V). Read it as 'C-I-V-I-L': the I sits before the V on the C side.
Real NEET questions
2016
A small signal voltage V(t) = V0 sin(wt) is applied across an ideal capacitor C. Which statement is correct?
A · Current I(t) lags voltage V(t) by 90°
B · Over a full cycle the capacitor C does not consume any energy from the voltage source ✓
C · Current I(t) is in phase with voltage V(t)
D · Current I(t) leads voltage V(t) by 180°
Solution: Step 1: For a pure capacitor, i = C·dV/dt = C·V0·w·cos(wt) = i0 sin(wt + 90°). So current LEADS voltage by 90°, not lags (A wrong), not in phase (C wrong), not 180° (D wrong). Step 2: Average power = Vrms·Irms·cos(phi). Here phi = 90°, and cos 90° = 0, so average power = 0. Step 3: Zero average power means over one full cycle the ideal capacitor takes in no net energy from the source - energy stored while charging is returned while discharging. So the correct statement is (B).
Solved Alternating Current NEET PYQs
Try the real previous-year questions from this chapter — each with the answer and a full solution.
By how much does current lead voltage in a pure capacitor?
By exactly 90°, which is a quarter of a full cycle. For a 50 Hz supply, one cycle is 0.02 s, so 90° means the current is ahead of the voltage by 0.005 s.
What is the formula that proves current leads voltage?
Start with V = V0 sin(wt). Current i = C·dV/dt = w·C·V0·cos(wt) = i0 sin(wt + 90°). The +90° inside the sine shows current is 90° ahead of voltage.
Does a real (non-ideal) capacitor also give exactly 90°?
Only an ideal capacitor gives exactly 90°. A real capacitor has a small resistance, so the lead is slightly less than 90°. For NEET, treat the capacitor as ideal and use 90°.
Why does the capacitor consume no power even though current flows?
Average power = Vrms·Irms·cos(phi). Since phi = 90° and cos 90° = 0, average power is zero. The current is 'wattless' - energy is stored then returned each cycle, with no net loss.
